Low energy electron beam proximity projection lithography (LEEPL) is one of the next generation exposure techniques taking the place of photolithography. LEEPL uses a stencil mask having a membrane of several hundreds of nm thickness formed with holes corresponding to device patterns. A “stencil mask” means a mask formed with holes passing through its membrane. No material exists in the spaces in the holes of the stencil mask.
In LEEPL, the mask is arranged just above a wafer so as to make a distance between the mask and wafer several tens of μm or so. Pattern parts of the mask are scanned by an electron beam of several keV to transfer the patterns on the wafer (T. Utsumi, Journal of Vacuum Science and Technology, B17, 2897 (1999)).
However, the mask for LEEPL has a problem of distortion of the patterns due to internal stress when the membrane is made larger in size and the membrane flexes by its weight. One method to solve the problem is to use diamond or another material having a high Young's modulus as the membrane material (see Japanese Unexamined Patent Publication (Kokai) No. 2001-77016). For decreasing the flex of the membrane due to its weight, the internal stress of the membrane has to be increased along with increase of the membrane size. Therefore, enlargement of the membrane is limited by itself.
Another method is the method of supporting a sub-sectioned membrane by a grid line (strut) structure. This is employed in masks used for SCALPEL (scattering with angular limitation in projection electron-beam lithography), PREVAIL (projection exposure with variable axis immersion lenses), and an EB stepper (for example, L. R. Harriott, Journal of Vacuum Science and Technology, B 15, 2130 (1997); H. C. Pfeiffer, Japanese Journal of Applied Physics, 34, 6658 (1995)).
FIG. 1 is a schematic view of an EB stepper mask currently proposed. As shown in FIG. 1, grid lines 11 divide and support a membrane 12. The membrane 12 is provided with holes (not shown) in device patterns.
The mask shown in FIG. 1 is made from for example an SOI (silicon on insulator or semiconductor on insulator) wafer comprised of a silicon wafer formed with a silicon active layer via a silicon oxide film. The silicon active layer on the surface of the SOI wafer is used as the membrane 12, while the grid lines 11 are formed by etching the silicon wafer from the rear surface of the silicon active layer.
According to the mask structure shown in FIG. 1, the membrane 12 is divided into small sections which are supported by the stiff grid lines 11. Therefore, the problem of the increase in deflection of the membrane along with the increase in the membrane size as observed in the mask described in Japanese Unexamined Patent Publication (Kokai) No. 2001-77016 etc. does not occur.
However, the mask structure with the grid lines 11 formed regularly in a square mesh as shown in FIG. 1 cannot be applied as it is to LEEPL. In LEEPL, first, a mask region corresponding to one or more chips is scanned by an electron beam.
After the exposure is finished, a wafer stage is moved by exactly a distance corresponding to the chip size or a whole multiple of the same and exposure performed again. This is repeated to expose chips arranged over the entire surface of the wafer (step and repeat exposure). As shown in FIG. 1, when the grid lines 11 are arranged in a square mesh, regions right below the grid lines cannot be exposed.
Therefore, rather than dividing the entire mask region uniformly in a mesh, the method of dividing the membrane of the mask 21 into four sub-regions A to D as shown in FIG. 2 and forming the grid lines (see FIG. 1) by these regions so that the meshes are offset may be considered. Here, each of the sub-regions A to D is a mask region corresponding to one or more chips (chip transfer region). The wafer stage is moved in units of these sub-regions.
FIG. 3 shows an example of arrangement of the grid lines 11 on the sub-regions A to D of the membrane of FIG. 2. In FIG. 3, the regions divided by the orthogonal x-axis and y-axis correspond to the sub-regions A to D of FIG. 2. As shown in FIG. 3, for convenience, the sub-regions are assumed to be squares of 10×10 blocks obtained by dividing them in a mesh.
In the example shown in FIG. 3, the 5×5 block parts surrounded by dotted lines in the sub-regions A to D correspond to single chips. When moving the wafer stage to the sub-regions A to D, the parts surrounded by the dotted lines are multiply exposed. The arrangement of the grid lines 11 in these sub-regions is a repetition of the arrangement of the grid lines 11 in the portions surrounded by the dotted lines (transfer regions).
As described above, since the regions right below the grid lines cannot be exposed, if linking the 5×5 blocks surrounded by the dotted lines with a 5 row×5 column table and summarizing which sub-region is exposed at each block (namely, in which sub-region a pattern can be formed), the result is shown in Table 1.
TABLE 1
In the case of a stencil mask, if forming a for example donut-like pattern, the center part surrounded by the pattern cannot be supported. Alternatively, when forming a long pattern etc. in one direction etc., the membrane will warp and the positional accuracy of the pattern will become lower. Therefore, the pattern is divided and a plurality of complementary masks are formed. The complementary masks are used for multiple exposure to transfer the pattern complementarily (complementary division).
Here, the “complementary masks” mean a plurality of masks formed with different patterns (complementarily divided patterns) comprised of parts of patterns obtained by dividing the pattern of a certain region. By exposing specific regions of the complementary masks superposed at the same place of the exposed object (usually a wafer), the pattern before division is restored and transferred to the exposed object.
For example, when arranging the grid lines shown in FIG. 3, as shown in Table 1, it is possible to form patterns in at least two sub-regions for each block. Therefore, it is possible to link two or more sub-regions with any position of a chip. By multiple exposure superposing four sub-regions on the same mask, it is possible to transfer any device pattern including a donut-like pattern to the wafer.
However, when combining the masks arranged with the grid lines as shown in FIG. 3 with certain types of alignment methods, problems may arise. With LEEPL, the mask and wafer are in proximity at a distance of several tens of μm, so an alignment optical system cannot be placed between the mask and the wafer.
Consequently, the through-the-reticle (TTR) alignment system as shown in FIG. 4 (Japanese Patent No. 3101582) is used. As shown in FIG. 4, the surface of the wafer 31 is formed with wafer-side alignment marks 32. On the other hand, the mask 33 is also formed with mask-side alignment marks 34. The mask-side alignment marks 34 can be either apertures passing through the membrane or recesses formed only in the surface of the membrane.
Alignment light strikes the wafer-side alignment marks 32 and the mask-side alignment marks 34. Light LW reflected from the wafer-side alignment marks 32 and Light LM reflected from the mask-side alignment marks 34 are detected. The relative position of the light LW and the light LM is used for alignment of the mask 33 and the wafer 31.
By arranging four alignment detection system (X1, X2, Y1, Y2) at the four corners of the mask as shown in FIG. 5 and performing alignment as shown in FIG. 4, distortion of the mask regions corresponding to the chips can be completely determined. According to the TTR alignment system, the alignment optical system is not placed between the mask and the wafer, so it becomes possible to constantly detect the alignment marks even during electron beam exposure and compensate for chip distortion in real time.
When forming grid lines on a mask in a square mesh as shown in FIG. 1 or FIG. 3, if performing alignment by the TTR alignment system, alignment becomes impossible under specific conditions. FIG. 6 is a cross-sectional view showing one of pattern formation regions surrounded by the grid lines 11.
As shown in FIG. 6, when a detection angle θ of alignment light L measured from a mask normal line direction z exceeds a specific critical angle θa determined by the interval and height of the grid lines 11 and positions of the alignment marks 34, the grid lines 11 and the alignment light L (light reflected from the mask-side alignment marks 34) interfere so the alignment light L can no longer be detected.